HDL #2 – Simulation and Testbench of Digital Circuits Design

March 28, 2026

Hello Robonesians, in the world of digital circuit design, whether for FPGAs or ASICs, there is one crucial stage before a design is realized into physical hardware: simulation. Simulation cannot be separated from the testbench, because the testbench is the “driving engine” that makes digital circuit design simulations possible.

For beginners, questions often arise:

What is simulation?
What is a testbench?
Why can’t a design be directly downloaded to an FPGA?
Why can a logically correct RTL still be wrong in hardware?

This article will explain the close relationship between simulation and testbench in a step-by-step and easy-to-understand manner, especially for those who are just starting to learn hardware description language (HDL), such as: VHDL, Verilog, and/or SystemVerilog.

Table of Contents

1. What is Simulation in Digital Design?

1.1 Definition of Simulation

Simulation is the process of running a digital circuit model (RTL, register transfer level) in simulator software to observe the circuit’s behavior over time, without building physical hardware. Simulation is equivalent to a “virtual testbed” before the hardware is built.

By doing simulations, we can:

View signal changes over time.
Ensures that the digital circuit logic works according to specifications.
Find bugs in HDL program code early, so they can be fixed quickly.
Save costs and time.

1.2 What is Simulated?

What is simulated is:

HDL program code is a digital circuit design or often called RTL (Register Transfer Level).
Digital logic model.
Behavior of sequential and/or combinational digital circuits.

Example:

Counter.
Adder (Half or Full).
Register.
FSM (Finite State Machine).
UART.
SPI.
Memory controller.
… and so forth

2. What is Testbench?

2.1 Definition of Testbench.

Testbench is a special HDL code used to:

Provides stimulus (input) to the digital circuit design (RTL) built using HDL program code.
Generates clock and reset.
Observing the design output.
Check whether the digital circuit output is correct or not.

2.2 Testbench Not Synthesized by Compiler.

Testbenches are not part of the digital circuit hardware design, so they are not synthesized by the compiler.

2.3 Why Can’t RTL Designs Be Simulated Alone?

Because digital circuit designs (RTL designs) created with HDL programming languages do not have natural input sources.

If you have any questions:

Where does the clock come from?
When is the reset active?
Who provides input values?
So the answer is: Testbench.

Without testbench:

There is no clock, so the sequential circuit does not run.
There is no input, so the output never changes.
The simulator doesn’t know what to test.

So it can be analogized, if the RTL design is a “machine”, then the testbench is the “machine operator and testing tool”.

3. Relationship between Simulation and Testbench

3.1 Fundamental Relationships

Simulation is a process, while a testbench is the controller of that process. Therefore, simulation and testbench are inseparable:

Table 1. Relationship between simulation and testbench

3.2 Illustration of Simulation and Testbench Concept

Imagine a washing machine:

Figure 1. Simulation and testbench concept

If the ” RTL design ” is a washing machine, then the ” testbench ” is the person operating the washing machine (the user). Meanwhile, the ” simulation ” is the actual working process of the washing machine. Without a person (the user) adjusting the operating buttons on the washing machine, the washing machine would never operate.

4. Simulation Flow with Testbench

The following are the stages of simulation using a testbench:

Create digital circuit design program code (VHDL/Verilog/SystemVerilog).
Create testbench program code.
RTL is instantiated in the testbench (DUT).
The testbench provides clock, reset, and input.
Time running simulator.
Output is observed or checked automatically

5. Why is Simulation Without Testbench Useless?

Without testbench:

There are no test scenarios.
There is no input variation.
There is no verification of results.

As a result:

New bugs were discovered while the hardware was being manufactured.
Debugging becomes difficult and expensive.
The risk of project failure increases

In the IC industry, errors that occur in digital circuit designs that pass the simulation stage can cause huge losses for the business.

6. Types of Simulations Using Testbench

6.1 Functional Simulation

The earliest stage is functional simulation, namely checking the logic function (gate level) of the digital system or circuit design.
At this stage, the simulation process does not take into account timing factors.

6.2 Timing Simulation

The next simulation stage is timing simulation, which is checking how long the delay is in sending signals in the digital system or circuit design.
Timing simulation is performed after the synthesis process or after the place & route process.

The testbench remains in use at all these stages.

7. Important Components of a Testbench

7.1 Clock Generator

Clock does not appear on its own.
The testbench must create the clock explicitly.

7.2 Reset Generator

Reset is used for:

Return to initial condition.
Avoid undefined values (X).

7.3 Stimulus Logic

The stimulus is:

Input value.
Sequence of events.
Test scenario

7.4 Design Under Test (DUT)

The DUT is the digital system or circuit design (RTL) being tested. The focus of testing during the simulation phase is on the DUT.

Figure 2. Illustration of a testbench

8. Why is the Testbench Not Synthesized?

Because the testbench uses the features:

Time delay.
Infinite loop.
File I/O.
Randomization

The above testbench features cannot be realized in hardware, so this is the reason why the testbench cannot be synthesized.

9. Common Mistakes of Digital System Designers

Didn’t create a testbench.
Assuming the RTL design is correct without simulation.
Do not use reset.
Didn’t test all scenarios.

Digital circuit design simulation using a testbench prevents all of these common possible errors.

10. Summary Explanation of Testbench

Simulation is the process of virtually executing a digital/RTL design.
Testbench is a simulation driver.
RTL cannot be tested without a testbench.
Simulation + testbench is the foundation of digital design.
The larger the digital system or circuit design, the more important the testbench.

By understanding the relationship between simulation and testbench, a novice engineer can not only “write HDL code”, but also understand the behavior of digital circuit design systematically and professionally.

11. Example of Testbench Program Code

11.1 VHDL Program Code – Digital System Design & Testbench

The following is an example of a VHDL code pair for designing a digital “counter” circuit and its testbench.

Program 1: VHDL program code for digital circuit design (counter.vhd)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        clk    : in  std_logic;
        reset  : in  std_logic;
        enable : in  std_logic;
        led    : out std_logic_vector(3 downto 0)
    );
end counter;

architecture rtl of counter is
    signal count : unsigned(3 downto 0);
begin

    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                count <= (others => '0');
            elsif enable = '1' then
                count <= count + 1;
            end if;
        end if;
    end process;

    led <= std_logic_vector(count);

end rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is

port (

clk : in std_logic;

reset : in std_logic;

enable : in std_logic;

led : out std_logic_vector(3 downto 0)

);

end counter;

architecture rtl of counter is

signal count : unsigned(3 downto 0);

begin

process(clk)

begin

if rising_edge(clk) then

if reset = '1' then

count <= (others => '0');

elsif enable = '1' then

count <= count + 1;

end if;

end process;

led <= std_logic_vector(count);

end rtl;

Program 2: VHDL program code for digital circuit design (tb_counter.vhd)

library ieee;
use ieee.std_logic_1164.all;

entity tb_counter is
end tb_counter;

architecture sim of tb_counter is

    signal clk    : std_logic := '0';
    signal reset  : std_logic := '0';
    signal enable : std_logic := '0';
    signal led    : std_logic_vector(3 downto 0);

begin

    -- DUT = counter.vhd (Program 1)
    dut: entity work.counter
        port map (
            clk    => clk,
            reset  => reset,
            enable => enable,
            led    => led
        );

    -- Clock generator (5 ns period)
    clk <= not clk after 5 ns;

    -- Stimulus & Reset
    stimulus: process
    begin
        reset <= '1';     // Reset
        wait for 20 ns;

        reset <= '0';     
        enable <= '1';    // Enable
        wait for 50 ns;

        enable <= '0';    // Hold (Unable)
        wait for 20 ns;

        enable <= '1';    // Enable
        wait for 30 ns;

        wait;
    end process;

end sim;

library ieee;

use ieee.std_logic_1164.all;

entity tb_counter is

end tb_counter;

architecture sim of tb_counter is

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal enable : std_logic := '0';

signal led : std_logic_vector(3 downto 0);

begin

-- DUT = counter.vhd (Program 1)

dut: entity work.counter

port map (

clk => clk,

reset => reset,

enable => enable,

led => led

);

-- Clock generator (5 ns period)

clk <= not clk after 5 ns;

-- Stimulus & Reset

stimulus: process

begin

reset <= '1'; // Reset

wait for 20 ns;

reset <= '0';

enable <= '1'; // Enable

wait for 50 ns;

enable <= '0'; // Hold (Unable)

wait for 20 ns;

enable <= '1'; // Enable

wait for 30 ns;

wait;

end process;

end sim;

Explanation:
Program 2 is the VHDL testbench code for the digital circuit design program “counter” (Program 1). In program 2, there is no input/output port declaration in its ENTITY block. Testbench components such as the design under test (DUT), clock generator, stimulus, and reset are available.

DUT = VHDL program code, counter.vhd (Program 1).
Clock generator = Clock signal is generated automatically every 5 ns.
Stimulus = Is a PROCESS program code block that carries out the stimulus test scenario Reset – enable – hold – enable.

11.2 Verilog Program Code – Digital System Design & Testbench

…..

11.3 SystemVerilog Program Code – Digital System Design & Testbench

….

Author

Taufiq Dwi Septian Suyadhi

Degrees from electronics and industrial engineering. Enthusiast on electronics, embedded systems, and robotics. Motivation: “Never ending learning and sharing valuable knowledge to the others”.